The present invention relates to a content addressable memory cell and an array which is composed of non-volatile storage elements and in which data is queried by a pair of differential data lines.
Content addressable memory cells and arrays are well known in the art. U.S. Pat. No. 5,949,696 discloses a differential volatile content addressable memory cell and an array made thereby.
Non-volatile content addressable memory cells and arrays are also well known in the art. U.S. Pat. No. 5,930,161 discloses a differential non-volatile content addressable memory cell and array using ferroelectric capacitors as storage elements. Referring to FIG. 1, there is shown a schematic block level diagram of a differential non-volatile content addressable memory array 8 as disclosed in FIG. 1 of U.S. Pat. No. 5,930,161. The array comprises a plurality of non-volatile content addressable memory cells 10 arranged in a plurality of rows and columns. In FIG. 1, the cells 10 are arranged in 4 rows by 4 columns. A word line (WL0 . . . WL3) connects all the cells 10 in the same row. A match line ML (ML0 . . . ML3) connects all the cells 10 in the same row and to an encoder 12. A pair of differential bit lines (BL0, BLN0 . . . BL3, BLN3) connects all the cells 10 in the same column. The data to which a comparison to determine if a match exists is supplied to the reference word storage and bit line drivers 14. The data is then supplied to the particular column along a pair of particular bit lines. All the match lines (ML0 . . . ML3) are connected to the encoder 12. When there is a match as determined by the particular match line going low (or high), the output of the encoder 12 indicates a hit as well as the address of the cell 10 where the match occurred.
Non-volatile floating gate storage elements are also well known in the art. These can be of the stacked gate type or the split gate type as exemplified by U.S. Pat. No. 5,029,130. In both the stack gate type or the floating gate type, charges on the floating gate affect the conduction of current in a channel in a semiconductor substrate. Typically, in one state, the floating gate is negatively charged such that no current flows in the channel. In a second state, when the floating gate is erased and there are no excess electrons, that state permits the conduction of current in the channel, when the floating gate is capacitively coupled to a positive voltage source.
A differential non-volatile content addressable memory cell comprises a pair of non-volatile storage elements in which each storage element has a first terminal, a second terminal, and a control terminal to control the flow of the current between the first terminal and the second terminal. Each of the storage elements has two non-volatile states. In a first state, a first current flows between the first terminal and the second terminal. In a second state, a second current less than the first current flows between the first terminal and the second terminal. A word line connects to the control terminals of the pair of non-volatile storage elements. A pair of differential data lines connects to the memory cell with one of the differential data lines connecting to the first terminal of one of the non-volatile storage elements and the other data line connecting to the first terminal of the other non-volatile storage element. A match line connects to the second terminal of each of the pair of non-volatile storage elements.
A differential non-volatile content addressable memory array using the foregoing described memory cell is also disclosed.